Electrochemical deposition processes are well-established in modern integrated circuit fabrication. The movement from aluminum to copper metal lines in the early years of the twenty-first century drove a need for more sophisticated electrodeposition processes and plating tools. Much of the sophistication evolved in response to the need for ever smaller current carrying lines in device metallization layers. These copper lines are formed by electroplating the metal into very thin, high-aspect ratio trenches and vias using a methodology commonly referred to as “damascene” processing.
Electrochemical deposition is now poised to fill a commercial need for sophisticated packaging and multichip interconnection technologies known generally as wafer level packaging (WLP) and through silicon via (TSV) electrical connection technology. These technologies present their own very significant challenges.
For example, these technologies require electroplating on a significantly larger feature size scale than most damascene applications. For various types of packaging features (e.g., TSV through chip connections, redistribution wiring, fan-out wiring, or flip-chip pillars), plated features are frequently, in current technology, greater than about 2 micrometers and typically 5-100 micrometers in height and/or width (for example, pillars may be about 50 micrometers). For some on-chip structures such as power busses, the feature to be plated may be larger than 100 micrometers. The aspect ratios of the WLP features are typically about 1:1 (height to width) or lower, while TSV structures can have very high aspect ratios (e.g., in the neighborhood of about 10:1 to 20:1).
Given the relatively large amount of material to be deposited, plating speed also differentiates WLP and TSV applications from damascene applications. Currently copper depositions rates of about 2.5 micrometers/minute are employed and solder plating rates of 3-5 micrometers/minute are used. In the future these rates are anticipated to increase to as high as 3.5 micrometers/min and 6 micrometers/min respectively. Further, independent of the plating rate, the plating must be conducted in a global and locally uniform manner on the wafer, as well as from one wafer to the next.
Still further, electrochemical deposition of WLP features may involve plating various combinations of metals such as the layered combinations or alloys of lead, tin, indium, silver, nickel, gold, palladium and copper.
While meeting each of these challenges, WLP electrofill processes must compete with conventionally less challenging and potentially less inexpensive pick and place (e.g. solder ball placement) or screen printing operations.